View TLE42754E_8244223.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

automotive power data sheet rev. 1.2, 2014-07-03 tle42754 low dropout linear fixed voltage regulator tle42754d tle42754g TLE42754E
pg-to252-5 pg-to263-5 pg-ssop-14 exposed pad type package marking tle42754d pg-to252-5 42754d tle42754g pg-to263-5 42754g TLE42754E pg-ssop-14 exposed pad 42754e data sheet 2 rev. 1.2, 2014-07-03 tle42754 low dropout linear fixed voltage regulator 1overview features ? output voltage 5 v 2% ? ouput current up to 450 ma ? very low current consumption ? power-on and undervoltage reset with programmable delay time ? reset low down to v q = 1 v ? very low dropout voltage ? output current limitation ? reverse polarity protection ? overtemperature protection ? suitable for use in automotive electronics ? wide temperature range from -40 c up to 150 c ? input voltage range from -42 v to 45 v ? green product (rohs compliant) ? aec qualified description the tle42754 is a monolithic integrated low-dropout voltage regulator in a 5-pin to-package, especially designed for automotive applications. an input voltage up to 42 v is regulated to an output voltage of 5.0 v. the component is able to drive loads up to 450 ma. it is short-circuit proof by the implemented current limitation and has an integrated overtemperat ure shutdown. a reset signal is generated for an output voltage v q,rt of typically 4.65 v. the power-on reset delay time can be programmed by the external delay capacitor.
tle42754 overview data sheet 3 rev. 1.2, 2014-07-03 dimensioning information on external components an input capacitor c i is recommended for compensation of line influences. an output capacitor c q is necessary for the stability of the control loop. circuit description the control amplifier compares a reference voltage to a volt age that is proportional to the output voltage and drives the base of the series transistor via a buffer. saturation control as a function of the load current prevents any oversaturation of the power element. the component also has a number of internal circuits for protection against: ? overload ? overtemperature ? reverse polarity
tle42754 block diagram data sheet 4 rev. 1.2, 2014-07-03 2 block diagram figure 1 block diagram res et generator bandgap reference protection circuits gnd d q ro i tle42754
tle42754 pin configuration data sheet 5 rev. 1.2, 2014-07-03 3 pin configuration 3.1 pin assignment tle42754d (pg-to 252-5) and tle4275 4g (pg-to263-5) figure 2 pin configuration (top view) 3.2 pin definitions and functions tle42754d (pg-to252-5) and tle42754g (pg- to263-5) pin symbol function 1i input for compensating line influences, a capacito r to gnd close to the ic terminals is recommended 2ro reset output open collector output; external pull-up resistor to a positive potential required; leave open if the reset function is not needed 3gnd tle42754g (pg-to263-5) only: ground internally con nected to tab 4d reset delay timing connect a ceramic capacitor to gnd for adjusting the reset delay time; leave open if the reset function is not needed 5q output block to gnd with a capacitor close to the ic terminals, respecting the values given for its capacitance c q and esr in the table ?functional range? on page 8 tab gnd ground connect to heatsink area aep02580 15 ro dq gnd gnd ro iep02528 d q pg-to252-5 (d-pak) pg-to263-5 (d2-pak)
tle42754 pin configuration data sheet 6 rev. 1.2, 2014-07-03 3.3 pin assignment tle42754 e (pg-ssop-14 exposed pad) figure 3 pin configuration (top view) 3.4 pin definitions and functions TLE42754E (pg-ssop-14 exposed pad) pin symbol function 1,3,5,7 n.c. not connected leave open or connect to gnd 2ro reset output open collector output; external pull-up resistor to a positive potential required; leave open if the reset function is not needed 4gnd ground 6d reset delay timing connect a ceramic capacitor to gnd for adjusting the reset delay time; leave open if the reset function is not needed 8,10,11,12, 14 n.c. not connected leave open or connect to gnd 9q output block to gnd with a capacitor close to the ic terminals, respecting the values given for its capacitance c q and esr in the table ?functional range? on page 8 13 i input for compensating line influenc es, a capacitor to gnd close to the ic terminals is recommended pad ? exposed pad connect to heatsink area; connect with gnd on pcb n.c. n.c. q n.c. n.c. n.c. i n.c. n.c. d n.c. gnd n.c. ro 1 2 3 4 5 6 7 14 9 10 11 12 13 8 pinconfig_ssop-14.svg
tle42754 general product characteristics data sheet 7 rev. 1.2, 2014-07-03 4 general product characteristics 4.1 absolute maximum ratings notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. table 1 absolute maximum ratings 1) -40 c t j 150c; all voltages with respect to ground, posi tive current flowing into pin (unless otherwise specified ) 1) not subject to production test, specified by design. parameter symbol values unit note / test condition number min. typ. max. input voltage v i -42 ? 45 v ? p_4.1.1 output voltage v q -0.3 ? 7 v ? p_4.1.2 reset output voltage v ro -0.3 ? 25 v ? p_4.1.3 reset delay voltage v d -0.3 ? 7 v ? p_4.1.4 temperature junction temperature t j -40 ? 150 c ? p_4.1.5 storage temperature t stg -50 ? 150 c ? p_4.1.6 esd absorption esd absorption v esd,hbm -2 ? 2 kv human body model (hbm) 2) 2) esd hbm test according aec-q100-002 - jesd22-a114 p_4.1.7 esd absorption v esd,cdm -500 ? 500 v charge device model (cdm) 3) 3) esd cdm test according esda stm5.3.1 p_4.1.8 esd absorption v esd,cdm -750 ? 750 v charge device model (cdm) 3) at corner pins p_4.1.9
tle42754 general product characteristics data sheet 8 rev. 1.2, 2014-07-03 4.2 functional range note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. table 2 functional range parameter symbol values unit note / test condition number min. typ. max. input voltage v i 5.5 ? 42 v ? p_4.2.1 output capacitor?s requirements for stability c q 22 ? ? f ? 1) 1) the minimum output capacitance requirement is appl icable for a worst case capacitance tolerance of 30% p_4.2.2 output capacitor?s requirements for stability esr(c q ) ??3 ? ? 2) 2) relevant esr value at f =10khz p_4.2.3 junction temperature t j -40 ? 150 c ? p_4.2.4
tle42754 general product characteristics data sheet 9 rev. 1.2, 2014-07-03 4.3 thermal resistance table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. tle42754d (pg-to252-5) junction to case 1) 1) not subject to production test, specified by design r thjc ? 3.7 ? k/w ? p_4.3.1 junction to ambient 1) r thja ? 27 ? k/w fr4 2s2p board 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 board with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. p_4.3.2 junction to ambient 1) r thja ? 110 ? k/w fr4 1s0p board, footprint only 3) 3) specified r thja value is according to jedec jesd 51-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm 3 board with 1 copper layer (1 x 70m cu). p_4.3.3 junction to ambient 1) r thja ? 57 ? k/w fr4 1s0p board, 300 mm 2 heatsink area on pcb 3) p_4.3.4 junction to ambient 1) r thja ? 42 ? k/w fr4 1s0p board, 600 mm 2 heatsink area on pcb 3) p_4.3.5 tle42754g (pg-to263-5) junction to case 1) r thjc ? 3.7 ? k/w ? p_4.3.6 junction to ambient 1) r thja ? 22 ? k/w fr4 2s2p board 2) p_4.3.7 junction to ambient 1) r thja ? 70 ? k/w fr4 1s0p board, footprint only 3) p_4.3.8 junction to ambient 1) r thja ? 42 ? k/w fr4 1s0p board, 300 mm 2 heatsink area on pcb 3) p_4.3.9 junction to ambient 1) r thja ? 33 ? k/w fr4 1s0p board, 600 mm 2 heatsink area on pcb 3) p_4.3.10 TLE42754E (pg-ssop-14 exposed pad) junction to case 1) r thjc ?7?k/w? p_4.3.11 junction to ambient 1) r thja ? 43 ? k/w fr4 2s2p board 2) p_4.3.12 junction to ambient 1) r thja ? 120 ? k/w fr4 1s0p board, footprint only 3) p_4.3.13 junction to ambient 1) r thja ? 59 ? k/w fr4 1s0p board, 300 mm 2 heatsink area on pcb 3) p_4.3.14 junction to ambient 1) r thja ? 49 ? k/w fr4 1s0p board, 600 mm 2 heatsink area on pcb 3) p_4.3.15
tle42754 block description and electrical characteristics data sheet 10 rev. 1.2, 2014-07-03 5 block description and el ectrical characteristics 5.1 voltage regulator the output voltage v q is controlled by comparing a portion of it to an internal reference and driving a pnp pass transistor accordingly. th e control loop stability depe nds on the outpu t capacitor c q , the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. to ensure stable operation, the output capacitor?s capacitance and its equivalent series resistor esr requirements given in the table ?functional range? on page 8 have to be maintained. for details see also the typical performance graph ?output capacitor series resistor esr ( c q ) versus output current i q ? on page 13 . as the output capacitor also has to buffer load steps it should be sized according to the application?s needs. an input capacitor c i is strongly recommended to compensate line in fluences. connect the capacitors close to the component?s terminals. a protection circuitry prevent the ic as well as the applic ation from destruction in ca se of catastrophic events. these safeguards contain an output current limitation, a reverse polarit y protection as well as a thermal shutdown in case of overtemperature. in order to avoid excessive power dissipation that coul d never be handled by the pass element and the package, the maximum output current is de creased at input voltages above v i =28v. the thermal shutdown circuit prevents the ic from i mmediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. after the chip has cooled down, the regulator restarts. this leads to an oscillatory behaviour of the output volt age until the fault is re moved. however, junction temperatures above 150 c are outside the maximum rating s and therefore significantly reduce the ic?s lifetime. the tle42754 allows a negative supply voltage. in this fault condition, small currents are flowing into the ic, increasing its junction temperature. this has to be considered for the thermal design, respecting that the thermal protection circuit is not operating during reverse polarity conditions. figure 4 voltage regulator bandgap reference gnd q i blockdiagram_voltager egulator.vsd saturation control current limitation temperature shutdown c q esr c } load supply c i regulated output voltage i q i i
tle42754 block description and electrical characteristics data sheet 11 rev. 1.2, 2014-07-03 table 4 electrical characteristics voltage regulator v i = 13.5v, -40c t j 150 c, all voltages with respect to ground , positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output voltage v q 4.9 5.0 5.1 v 1 ma < i q < 450 ma 9v < v i < 28 v p_5.1.1 output voltage v q 4.9 5.0 5.1 v 1 ma < i q < 400 ma 6v < v i < 28 v p_5.1.2 output voltage v q 4.9 5.0 5.1 v 1 ma < i q < 200 ma 6v < v i < 40 v p_5.1.3 output current limitation i q,max 450 ? 1100 ma v q = 4.8v p_5.1.4 load regulation steady-state ? v q,load -30 -15 ? mv i q = 5ma to 400ma v i = 8 v p_5.1.5 line regulation steady-state ? v q,line ?5 15mv v i = 8 v to 32 v i q = 5 ma p_5.1.6 dropout voltage 1) v dr = v i - v q 1) measured when the output voltage v q has dropped 100mv from the nominal value obtained at v i = 13.5v v dr ?250500mv i q = 300 ma p_5.1.7 power supply ripple rejection 2) 2) not subject to production test, specified by design psrr ?60? db f ripple = 100 hz v ripple = 0.5 vpp p_5.1.8 temperature output voltage drift d v q /d t ? 0.5 ? mv/k ? p_5.1.9 overtemperature shutdown threshold t j,sd 151 ? 200 c t j increasing 2) p_5.1.10 overtemperature shutdown threshold hysteresis t j,sdh ?20? c t j decreasing 2) p_5.1.11
tle42754 block description and electrical characteristics data sheet 12 rev. 1.2, 2014-07-03 typical performance characteristics voltage regulator output voltage v q versus junction temperature t j output current limitation i q,max versus input voltage v i power supply ripple rejection psrr versus ripple frequency f r line regulation ? v q,line versus input voltage change ? v i 01_vq_tj.vsd 4,60 4,70 4,80 4,90 5,00 5,10 5,20 -40 0 40 80 120 160 t j [c] v q [v] v i = 13.5 v i q = 50 ma 02_iq_vi.vsd 0 100 200 300 400 500 600 700 800 900 1000 0 1020304050 v i [v] i q,max [ma] t j = -40 c t j = 150 c t j = 25 c 03_psrr_fr.vsd 0 10 20 30 40 50 60 70 80 90 100 0,01 0,1 1 10 100 1000 f [khz] psrr [db] t j = 150 c t j = 25 c t j = -40 c i q = 10 ma c q = 22 f ceramic v i = 13.5 v v ripple = 0.5 vpp 04_dvq_dvi.vsd 0 1 2 3 4 5 6 7 8 9 0 10203040 v i [v] v q [mv] t j = 150 c t j = 25 c t j = -40 c
tle42754 block description and electrical characteristics data sheet 13 rev. 1.2, 2014-07-03 load regulation ? v q,load versus output current change ? i q output capacitor series resistor esr ( c q ) versus output current i q dropout voltage v dr versus junction temperature t j 05_dvq_diq.vsd -25 -20 -15 -10 -5 0 0 100 200 300 400 500 i q [ma] v q [mv] v i = 8 v t j = -40 c t j = 25 c t j = 150 c 06_esr_iq.vsd 0,01 0,1 1 10 100 1000 0 100 200 300 400 500 i q [ma] esr(c q ) [ ] c q = 22 f t j = -40..150 c v i = 6..28 v stable region unstable region 07_vdr_tj.vsd 0 50 100 150 200 250 300 350 400 450 500 -40 0 40 80 120 160 t j [c] v dr [mv] i q = 400 ma i q = 300 ma i q = 100 ma i q = 10 ma
tle42754 block description and electrical characteristics data sheet 14 rev. 1.2, 2014-07-03 5.2 current consumption table 5 electrical characteristics current consumption v i = 13.5v, -40c t j 150 c, positive current flowing in to pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. current consumption i q = i i - i q i q ? 150 200 a i q = 1 ma t j = 25 c p_5.2.1 current consumption i q = i i - i q i q ? 150 220 a i q = 1 ma t j = 85 c p_5.2.2 current consumption i q = i i - i q i q ?510ma i q = 250 ma p_5.2.3 current consumption i q = i i - i q i q ?1525ma i q = 400 ma p_5.2.4
tle42754 block description and electrical characteristics data sheet 15 rev. 1.2, 2014-07-03 typical performance characte ristics current copnsumption current consumption i q versus output current i q ( i q low ) current consumption i q versus output current i q current consumption i q versus input voltage v i 08_iq_iq_iqlow.vsd 0 1 2 3 4 5 6 7 0 50 100 150 200 i q [ma] i q [ma] t j = 150 c t j = 25 c v i = 13.5 v 09_iq_iq.vsd 0 5 10 15 20 25 30 0 100 200 300 400 500 i q [ma] i q [ma] t j = 150 c t j = 25 c v i = 13.5 v 10_iq_vi.vsd 0 10 20 30 40 50 60 0 10203040 v i [v] i q [ma] r load = 12.5 r load = 500
tle42754 block description and electrical characteristics data sheet 16 rev. 1.2, 2014-07-03 5.3 reset function the reset function provides several features: output undervoltage reset: an output undervoltage condition is indicated by setting the reset output ro to ?low?. this signal might be used to reset a microcontroller during low supply voltage. power-on reset delay time: the power-on reset delay time t rd allows a microcontoller and oscillator to start up. this delay time is the time frame from exceeding the reset switching threshold v rt until the reset is released by switching the reset output ?ro? from ?low? to ?high?. the power-on reset delay time t rd is defined by an external delay capacitor c d connected to pin d charged by the delay capacitor charge current i d,ch starting from v d =0v. if the application needs a power-on reset delay time t rd different from the value given in power on reset delay time , the delay capacitor?s value can be derived from the specified values in power on reset delay time and the desired power-on delay time: (1) with ? c d : capacitance of the delay capacitor to be chosen ? t rd,new : desired power-on reset delay time ? t rd : power-on reset delay time specified in this datasheet for a precise calculation also take the dela y capacitor?s tolerance into consideration. reset reaction time: the reset reaction time avoids that short undervoltage spikes trigger an unwanted reset ?low? signal. the reset reaction rime t rr considers the intern al reaction time t rr,int and the discharge time t rr,d defined by the external delay capacitor c d (see typical performance graph for details). hence, the total reset reaction time becomes: (2) with ? t rr : reset reaction time ? t rr,int : internal reset reaction time ? t rr,d : reset discharge reset output pull-up resistor r ro : the reset output ro is an open collector output re quiring an external pull-up resistor to a voltage v io , e.g. v q . in table 6 ?electrical characteri stics reset function? on page 19 a minimum value for the external resistor r ro is given for the case it is connected to v q or to a voltage v io < v q . if the pull-up resistor shall be connected to a voltage v io > v q , use the following formula: (3) c d t rd new , t rd ---------------- 47nf = t rr t rd int , t rr d , + = r ro 5k v q ---------- - v io =
tle42754 block description and electrical characteristics data sheet 17 rev. 1.2, 2014-07-03 figure 5 block diagram reset function gnd q i blockdiagram_reset.vsd supply ro v dst in t. supply i d, ch i dr, dsch v rt control d c d reset c q vdd micro- controller gnd i ro r ro
tle42754 block description and electrical characteristics data sheet 18 rev. 1.2, 2014-07-03 figure 6 timing diagram reset v i t v q t v rt v ro timingdiagram_reset.vs t v ro,low 1 v 1v t rr,total t rd thermal shutdown input voltage dip t rr,total t rd t rd t < t rr,total t rd under- voltage spike at output over- load t r r ,to ta l v drl v du t v d
tle42754 block description and electrical characteristics data sheet 19 rev. 1.2, 2014-07-03 table 6 electrical characteristics reset function v i = 13.5v, -40c t j 150 c, all voltages with respect to ground , positive current flowing into pin (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. output undervoltage reset output undervoltage reset switching thresholds v rt 4.5 4.65 4.8 v v q decreasing p_5.3.1 reset output ro reset output low voltage v ro,low ?0.20.4v1v v q v rt ; i ro = 0.2 ma p_5.3.2 reset output sink current capability i ro,max 0.2 ? ? ma 1 v v q v rt ; v ro = 5 v p_5.3.3 reset output leakage current i ro,leak ?010a v ro = 5 v p_5.3.4 reset output external pull-up resistor to v q r ro 5??k ? 1v v q v rt ; v ro 0.4 v p_5.3.5 reset delay timing power on reset delay time t rd 10 16 22 ms c d = 47 nf p_5.3.6 upper delay switching threshold v du ? 1.8 ? v ? p_5.3.7 lower delay switching threshold v drl ? 0.65 ? v ? p_5.3.8 delay capacitor charge current i d,ch ?5.5?a v d = 1 v p_5.3.9 delay capacitor reset discharge current i d,dch ? 100 ? ma v d = 1 v p_5.3.10 delay capacitor discharge time t rr,d ? 0.5 1 s calculated value: t rr,d = c d *( v du - v drl )/ i d,dch c d = 47 nf p_5.3.11 internal reset reaction time t rr,int ?47s c d = 0 nf 1) 1) parameter not subject to production test; specified by design p_5.3.12 reset reaction time t rr,total ? 4.5 8 s calculated value: t rr,total = t rr,int + t rr,d c d = 47 nf p_5.3.13
tle42754 block description and electrical characteristics data sheet 20 rev. 1.2, 2014-07-03 typical performanc e characteristics undervoltage reset switching threshold v rt versus t j power on reset delay time t rd versus junction temperature t j power on reset delaytime t rd versus capacitance c d internal reset reaction time t rr,int versus junction temperature t j 11_vrt_tj.vsd 4,4 4,5 4,6 4,7 4,8 4,9 5 -40 0 40 80 120 160 t j [c] v rt [v] 12_trd_tj.vsd 0 2 4 6 8 10 12 14 16 18 20 -40 0 40 80 120 160 t j [c] t rd [ms] c d = 47 nf 13_trd_cd.vsd 0 10 20 30 40 50 60 70 80 90 0 50 100 150 200 250 c d [nf] t rd [ms] t j = -40 c t j = 25 c t j = 150 c 14_trrint_tj.vsd 0 0,5 1 1,5 2 2,5 3 3,5 -40 0 40 80 120 160 t j [c] t rr,int [s]
tle42754 block description and electrical characteristics data sheet 21 rev. 1.2, 2014-07-03 delay capacitor discharge time t rr,d versus junction temperature t j 15_trrd_tj.vsd 0 0,1 0,2 0,3 0,4 0,5 0,6 -40 0 40 80 120 160 t j [c] t rr,d [s] c d = 47 nf
tle42754 application information data sheet 22 rev. 1.2, 2014-07-03 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 6.1 application diagram figure 7 application diagram 6.2 selection of external components 6.2.1 input pin the typical input circuitry for a linear voltage regulator is shown in the application diagram above. a ceramic capacitor at the input, in the range of 100nf to 470nf, is recommended to filter out the high frequency disturbances imposed by the line e.g. iso pulses 3a/b. this capacitor must be placed very close to the input pin of the linear voltage regulator on the pcb. an aluminum electrolytic capacitor in the range of 10 f to 470f is recommended as an input buffer to smooth out high energy pulses, such as iso pulse 2a. this capaci tor should be placed close to the input pin of the linear voltage regulator on the pcb. an overvoltage suppressor diode can be used to furthe r suppress any high voltag e beyond the maximum rating of the linear voltage regulator and protect th e device against any damage due to over-voltage. the external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances. 6.2.2 output pin an output capacitor is mandatory for th e stability of linear voltage regulators. the requirement to the output capacitor is given in ?functional range? on page 8 . the graph ?output capacitor series resistor esr ( c q ) versus output current i q ? on page 13 shows the stable operation range of the device. reset generator bandgap reference protection circuits gnd d q ro i tle42754 supply 100 nf 10 f c i1 c i2 regulated output voltage i q c q 22f (esr<3 ? ) c d 47 nf <45v d i load (e.g. micro controller) gnd i i r ro 5k ?
tle42754 application information data sheet 23 rev. 1.2, 2014-07-03 tle42754 is designed to be stable with extremely low esr capacitors. according to the automotive environment, ceramic capacitors with x5r or x7r dielectrics are recommended. the output capacitor should be placed as close as possible to the regulat or?s output and gnd pins and on the same side of the pcb as the regulator itself. in case of rapid transients of input voltage or load curr ent, the capacitance should be dimensioned in accordance and verified in the re al application that t he output stability requ irements are fulfilled. 6.3 thermal considerations knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: (4) with ? p d : continuous power dissipation ? v i : input voltage ? v q : output voltage ? i q : output current ? i q : quiescent current the maximum acceptable thermal resistance r thja can then be calculated: (5) with ? t j,max : maximum allowed junction temperature ? t a : ambient temperature based on the above calculation the proper pcb type and the necessary heat sink area can be determined with reference to the specification in ?thermal resistance? on page 9 . example application conditions: v i = 13.5 v v q = 5 v i q = 250 ma t a = 85 c calculation of r thja,max : p d =( v i ? v q ) ? i q + v i ? i q = (13.5 v ? 5 v) ? 250 ma + 13.5 v ? 10 ma = 2.125 w + 0.135 w =2.26w p d v i v q ? () i q v i i q + = r thja max , t jmax , t a ? p d --------------------------- - =
tle42754 application information data sheet 24 rev. 1.2, 2014-07-03 r thja,max =( t j,max ? t a ) / p d = (150 c ? 85 c) / 2.26 w =28.76k/w as a result, the pcb design must ensure a thermal resistance r thja lower than 28.76 k/w. by considering tle42754g (pg-to263-5 package) and according to ?thermal resistance? on page 9 , only the fr4 2s2p board is applicable. 6.4 reverse polarity protection tle42754 is self protected against reve rse polarity faults and allows negati ve supply voltage. external reverse polarity diode is not needed. however, the absolute maximum ratings of the device as specified in ?absolute maximum ratings? on page 7 must be kept. the reverse voltage causes several sma ll currents to flow into the ic henc e increasing its junction temperature. as the thermal shut down circuitry does not work in the re verse polarity condition, designers have to consider this in their thermal design.
tle42754 package outlines data sheet 25 rev. 1.2, 2014-07-03 7 package outlines figure 8 pg-to252-5 1) includes mold flashes on each side. 4.56 0.25 m a 6.5 5.7 max. ?.1 per side 0.15 max. -0.2 6.22 ?.5 9.98 (4.24) 1 a 1.14 5 x 0.6 ?.15 0.8 ?.1 +0.15 -0.05 0.1 b -0.04 +0.08 0...0.15 0.51 min. 0.5 b 2.3 -0.10 0.5 +0.05 -0.04 +0.08 (5) -0.01 0.9 +0.20 b 1) all metal surfaces tin plated, except area of cut.
tle42754 package outlines data sheet 26 rev. 1.2, 2014-07-03 figure 9 pg-to263-5 b a 0.25 m ?.2 gpt09113 10 8.5 1) (15) ?.2 9.25 ?.3 1 0...0.15 5 x 0.8 ?.1 ?.1 1.27 4.4 b 0.5 ?.1 ?.3 2.7 4.7 ?.5 2.4 1.7 0...0.3 a 1) 7.55 4 x all metal surfaces tin plated, except area of cut. metal surface min. x = 7.25, y = 6.9 typical 1) 0.1 b 0.1 0.05 8? max.
tle42754 package outlines data sheet 27 rev. 1.2, 2014-07-03 figure 10 pg-ssop-14 exposed pad green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). 1 7 14 8 14 17 8 14x 0.25 ?.05 ?.05 2) m 0.15 d c a-b 0.65 c s tand off 0.05 (1.45) 1.7 max. 0.0 8 c a b 4.9 ?.1 1) a-b h 0.1 2x 1) doe s not incl u de pl as tic or met a l protr us ion of 0.15 m a x. per s ide 2) le a d width c a n b e 0.61 m a x. in d a m ba r a re a bottom view ?.2 3 ?.2 2.65 ?.2 d h 6 14x 0.64 ?.25 3 .9 ?.1 1) 0. 3 5 x 45 0.1 hd 2x 0.2 c +0.06 0.19 8 max. index m a rking expo s ed diep a d s eating plane 6 x 0.65 = 3 .9 for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
tle42754 revision history data sheet 28 rev. 1.2, 2014-07-03 8 revision history version date changes 1.2 2014-07-03 ?application information? on page 22 added. pg-ssop-14 ep package outline updated. 1.11 2012-01-20 page 19 : condition of parameter delay capacitor discharge time , internal reset reaction time and reset reaction time corrected. parameters are valid for all package variants. no need to limit the measurement conditions. coverpage updated. 1.1 2008-09-24 data sheet updated with new package variant in pg-ssop-14 exposed pad: in ?overview? on page 2 package graphic and sales name with marking added in table 4.3 ?thermal resistance? on page 9 values for package pg-ssop-14 exposed pad added in ?package outlines? on page 25 outlines for package pg-ssop-14 exposed pad added 1.0 2008-05-29 final data sheet
edition 2014-07-03 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

▲Up To Search▲

Price & Availability of TLE42754E

	To Download TLE42754E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .